nRF54LM20B System-on-Chip with integrated NPU

Ultra-low-power wireless SoC with integrated Axon NPU

The nRF54L Series offers SoCs that combine an efficient MCU with ultra-low-power wireless connectivity. The nRF54LM20B provides the largest memory option in the series, with 2 MB NVM and 512 KB RAM. It features an extended set of peripherals, high-speed USB, and is available with up to 66 GPIOs.

The nRF54LM20B also includes an integrated Axon NPU, increasing the speed and efficiency of on-device AI inferencing up to 15x compared to using the CPU for the same task.

nRF54LM20B supports Bluetooth LE, Matter, Thread, Zigbee, and 2.4 GHz proprietary protocols with data rates up to 4 Mbps for low-latency applications. It also supports Bluetooth Channel Sounding, Bluetooth Mesh, and Wi-Fi with nRF70 Series companion ICs.

Performance highlights

  • Processing efficiency and performance: 193 CoreMark/mA @ 3 V, 503 CoreMark®
  • Enhanced edge AI capabilities thanks to integrated Axon NPU
  • Radio power consumption: 3.4 mA for RX and 4.8 mA for TX @ 0 dBm (@ 3 V)
  • Sleep modes power consumption: from 0.7 μA to 4.0 μA (@ 3 V)
  • Maximum TX power: +8 dBm (CSP) / +7 dBm (QFN) 
  • Sensitivity: -96 dBm (1M Bluetooth LE), -101 dBm (802.15.4)
  • Optimized for the lowest total average current


Key benefits

  • Increased speed and efficiency of AI inference tasks 
  • Reduced design complexity, size, and cost
  • Reliable and robust wireless connectivity
  • Extended battery life enabled by lower power consumption
  • Built-in security features supporting compliance with regulations
  • Broad range of MCU feature sets across the series


The nRF54L Series

Key Features
  • 128 MHz Arm® Cortex®-M33
  • 128 MHz integrated Axon NPU 
  • 2 MB NVM and 512 KB RAM
  • Ultra-low-power multiprotocol 2.4 GHz radio 
  • 1x High-speed SPI/UART
  • 6x SPI/TWI/UART
  • High-speed USB
  • ADC, TDM, PDM, NFC, PWM, and QDEC
  • Global RTC available in System OFF
  • 128 MHz RISC-V coprocessor with support for SoftPeripherals
  • Up to 66 GPIOs
  • TrustZone® isolation, tamper detection, and cryptographic engine with side-channel leakage protection
  • Package options: CSP98, CSP61, QFN52
Documentation
Datasheet

Reference layout

FCCSP package

Selected version
0.6

Changelog:

0.6

  • FB2 removed
  • C12 updated to 1.5pF
  • L4 changed to 3.3nH
  • C6 changed to 4.7µF
  • C7 changed to N.C.
  • X2 changed to X1
  • X1 changed to X2

0.5

  • Pad D1 on nRF54LM20 connected to GND on top layer
  • Removed thermal relief on C3, C12 and C13

0.4

  • C9 removed
  • L5 and C8 added
  • L2 changed to 3.6nH
  • L3 changed to 4.7nH
  • L4 changed to 2.2nH
  • C3 and C12 changed to 1.2pF
  • C13 changed to DNM
  • C6 changed to 4.7µF
  • R2 changed to 200ohm
  • Updated component placement on C8, C14, L5 ,FB2 and X2 to match the schematic
  • Removed GND on inner layers below the 50 ohm impedance trace

0.3